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product specification ps014004-1106 z80180 microprocessor unit ps014004-1106 zilog worldwide headquarters ? 532 race street ? san jose, ca 95126 telephone: 408.558.8500 ? fax: 408.558 . 8300 ?www. zilog .com
ps014004-1106 this publication is subject to replacement by a later edition. to determine whether a later edition exists, or to reques t copies of publications, contact: zilog worldwide headquarters 532 race street san jose, ca 95126-3432 telephone: 408.558.8500 fax: 408.558.8300 www.zilog.com zilog is a registered trademark of zilog inc. in th e united states and in other countries. all other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. document disclaimer ?2006 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. devices sold by zilog, inc. are covered by warranty and limitation of liability provisions a ppearing in the zilog, inc. terms and conditions of sale. zilog, inc. makes no warranty of merchantabilit y or fitness for any pur pose. except with the express written approval of zilog, use of informati on, devices, or technology as critical components of life support systems is not authorized. no licens es are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
ps014004-1106 z80180 microprocessor unit iii revision history each instance in the following table reflects a change to this document from its previous revision. to see more detail, click the appropriate link in the table below. date revision level description page no november 2006 04 updated dc characteristics table and minor edits done throughout the document. all
ps014004-1106 z80180 microprocessor unit iv
ps014004-1106 z80180 microprocessor unit v table of contents overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 multiplexed pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 asci register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 asci registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 asci transmit data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 asci receive registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 asci channel control register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 asci channel control register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 asci status register 0, 1 (stat0, 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 csio control/status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 csio transmit/receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 timer data register channel 0l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 timer data register channel 0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 timer reload register 0l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 timer reload register 0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 timer control register (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 asci extension control register channels 0 and 1 . . . . . . . . . . . . . . . . . . . . . 50 asext0 and asext1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 timer data register channel 1l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 timer data register channel 1h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 timer reload register channel 1l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 timer reload register channel 1h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 free running counter i/o address = 18h . . . . . . . . . . . . . . . . . . . . . . . . . 54
ps014004-1106 z80180 microprocessor unit vi dma source address register channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 dma source address register, channel 0l . . . . . . . . . . . . . . . . . . . . . . . . 54 dma source address register, channel 0h . . . . . . . . . . . . . . . . . . . . . . . 55 dma source address register channel 0b . . . . . . . . . . . . . . . . . . . . . . . . 55 dma destination address register channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . 55 dma destination address register channel 0l . . . . . . . . . . . . . . . . . . . . . 56 dma destination address register channel 0h . . . . . . . . . . . . . . . . . . . . . 56 dma destination address register channel 0b . . . . . . . . . . . . . . . . . . . . . 56 dma byte count register channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 dma byte count register channel 0l . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 dma byte count register channel 0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 dma byte count register channel 1l . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 dma byte count register channel 1h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 dma memory address register channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 dma memory address register, channel 1l . . . . . . . . . . . . . . . . . . . . . . . 59 dma memory address register, channel 1h . . . . . . . . . . . . . . . . . . . . . . . 60 dma memory address register, channel 1b . . . . . . . . . . . . . . . . . . . . . . . 60 dma i/o address register channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 dma i/o address register channel 1l . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 dma i/o address register channel 1h . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 dma i/o address register channel 1b . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 dma status register (dstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 dma mode register (dmode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 dma/wait control register (dcntl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 interrupt vector low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 int/trap control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 refresh control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 mmu common base register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 mmu bank base register (bbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 mmu common/bank area register (cbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 operation mode control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 i/o control register (icr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
z80180 microprocessor unit 1 ps014004-1106 overview overview features the key features of z80180 ? microprocessor unit (mpu) include: ? code compatible with zilog z80 ? cpu ? extended instructions ? two dma channels ? low power-down modes ? on-chip interrupt controllers ? three on-chip wait-state generators ? on-chip oscillator/generator ? expanded mmu addressing (up to 1 mb) ? clocked serial i/o port ? two 16-bit counter/timers ? two uarts ? clock speeds: 6 mhz, 8 mhz, and 10 mhz ? 6 mhz version supports 6.144 mhz cpu clock operation ? operating range: 5 v ? operating temperature range: 0 oc to +70 oc ? three packaging styles ? 68-pin plcc ? 64-pin dip ? 80-pin qfp general description the z80180 ? is an 8-bit mpu which provides the bene fits of reduced system costs and also provides full backward compatibility with existing zilog z80 devices. reduced system costs are obtained by incorp orating several key system functions on-chip with the cpu. these key functions include i/o devices such as dma, uart, and timer
z80180 microprocessor unit 2 ps014004-1106 overview channels. also included on-chip are wait-state genera tors, a clock oscillator, and an interrupt controller. the z80180 ? is housed in 80-pin qfp, 68-p in plcc, and 64-pin dip packages. all signals with an overline are active low. for example, b/w , in which word is active low); and b /w, in which byte is active low. power connections follow conventio nal descriptions as listed in table 1 . table 1. power connection conventions figure 1. z80180 functional block diagram connection circuit device power v cc v dd ground gnd v ss note: processor power controller 16-bit 8-bit mmu dmacs (2) clocked 16-bit programmable reload timers (2) uarts (2) decode a b txa1?0 rxa1?0 address bus data bus serial i/o b
z80180 microprocessor unit 3 ps014004-1106 overview pin configuration figure 2. z80180 64-pin dip configuration v ss xtal extal wait busack busreq reset nmi int0 int1 int2 st a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 v cc phi rd wr m1 e mreq iorq rfsh halt tend1 dreq1 cks rxs/cts1 txs cka1/tend0 rxa1 txa1 cka/dreq0 rxa0 txa0 dcd0 cts0 rts0 d7 d6 d5 d4 d3 d2 d1 d0 v ss 33 64 z80180 64-pin 32 1
z80180 microprocessor unit 4 ps014004-1106 overview z80180 68-pin plcc pin configuration figure 3. z80180 68-pin plcc configuration nmi reset busreq busack wa i t extal xtal v ss v ss phi rd wr m1 e mreq iorq rfsh 60 44 10 26 int0 int1 int2 st a0 a1 a2 a3 v ss a4 a5 a6 a7 a8 a9 a10 a11 43 27 61 9 z80180 68-pin plcc 1 halt tendi dreqi cks rxs/ cts1 txs cka1/ tend0 rxa1 test txa1 cka0/ dreq0 rxa0 txa0 dcd0 cts0 rts0 d7 a12 a13 a14 a15 a16 a17 a18/t out v cc a19 v ss d0 d1 d2 d3 d4 d5 d6
z80180 microprocessor unit 5 ps014004-1106 overview figure 4. z80180 80-pin qfp configuration table 2. pin status during reset busack and sleep pin number and package type default function secondary function pin status qfp plcc dip reset busack sleep 19 8 nmi in in in 2nc 40 65 iorq mreq e m1 wr rd phi v ss v ss xtal n/c extal wait busack busreq reset nmi n/c n/c int0 int1 int2 st a0 a1 a2 a3 v ss a4 n/c a5 a6 a7 a8 a9 a10 a11 n/c n/c a12 rfsh n/c n/c halt tend1 dreq1 cks rxs/cts1 txs cka1/tend0 rxa1 test txa1 n/c cka0/dreq0 rxa0 txa0 dcd0 cts0 rts0 d7 n/c n/c d6 510152024 60 55 50 45 41 64 z80180 80-pin qfp 1 d5 d4 d3 d2 d1 d0 v ss a19 v cc a18/t out nc a17 a16 a15 a14 a13
z80180 microprocessor unit 6 ps014004-1106 overview 3nc 410 9 int0 in in in 511 10 int1 in in in 612 11 int2 in in in 713 12 st 1 ? 1 814 13 a0 3t 3t 1 915 14 a1 3t 3t 1 10 16 15 a2 3t 3t 1 11 17 16 a3 3t 3t 1 12 18 v ss gnd gnd gnd 13 19 17 a4 3t 3t 1 14 nc 15 20 18 a5 3t 3t 1 16 21 19 a6 3t 3t 1 17 22 20 a7 3t 3t 1 18 23 21 a8 3t 3t 1 19 24 22 a9 3t 3t 1 20 25 23 a10 3t 3t 1 21 26 24 a11 3t 3t 1 22 nc 23 nc 24 27 25 a12 3t 3t 1 25 28 26 a13 3t 3t 1 26 29 27 a14 3t 3t 1 27 30 28 a15 3t 3t 1 28 31 29 a16 3t 3t 1 29 32 30 a17 3t 3t 1 30 nc 31 33 31 a18 t out 3t 3t 1 table 2. pin status during reset bu sack and sleep(continued) (continued) pin number and package type default function secondary function pin status qfp plcc dip reset busack sleep
z80180 microprocessor unit 7 ps014004-1106 overview 32 34 32 v cc v cc v cc v cc 33 35 a19 3t 3t 1 34 36 33 v ss gnd gnd gnd 35 37 34 d0 3t 3t 3t 36 38 35 d1 3t 3t 3t 37 39 36 d2 3t 3t 3t 38 40 37 d3 3t 3t 3t 39 41 38 d4 3t 3t 3t 40 42 39 d5 3t 3t 3t 41 43 40 d6 3t 3t 3t 42 nc 43 nc 44 44 41 d7 3t 3t 3t 45 45 42 rts0 1out1 46 46 43 cts0 in out in 47 47 44 dcd0 in in in 48 48 45 txa0 1 out out 49 49 46 rxa0 in in in 50 50 47 cka0 dreq0 3t out out 51 nc 52 51 48 txa1 1 out out 53 52 test 54 53 49 rxa1 in in in 55 54 50 cka1 tend0 3t in in 56 55 51 txs 1 out out 57 56 52 rxs cts1 in in in 58 57 53 cks 3t i/o i/o 59 58 54 dreq1 in 3t in 60 59 55 tend1 1out1 table 2. pin status during reset bu sack and sleep(continued) (continued) pin number and package type default function secondary function pin status qfp plcc dip reset busack sleep
z80180 microprocessor unit 8 ps014004-1106 overview pin descriptions a 0?a19. address bus (output, active high, 3-state) ? a 0 ?a 19 form a 20-bit address bus. the address bus provides the address for memory data bus exchanges, up to 1 mb, and i/o data bus exchanges, up to 64 kb. the address bus enters a high-impedance state during reset and external bus acknowle dge cycles. address line a18 is multiplexed with the output of programmable reload timer (prt) channel 1 ( t out , selected as address output on reset) and address line a19 is not available in dip versions of the z80180. 61 60 56 halt 11 0 62 nc 63 nc 64 61 57 rfsh 1outout 65 62 58 iorq 13t 1 66 63 59 mreq 13t 1 67 64 60 e 0 out out 68 65 61 m1 11 1 69 66 62 wr 13t 1 70 67 63 rd 13t 1 71 68 64 phi out out out 72 1 1 v ss gnd gnd gnd 73 2 v ss gnd gnd gnd 74 3 2 xtal out out out 75 nc 76 4 3 extal in in in 77 5 4 wait in in in 78 6 5 busack 1outout 79 7 6 busreq in in in 80 8 7 reset in in in table 2. pin status during reset bu sack and sleep(continued) (continued) pin number and package type default function secondary function pin status qfp plcc dip reset busack sleep
z80180 microprocessor unit 9 ps014004-1106 overview busac k ? bus acknowledge (output, active low). busack indicates the requesting device, the mpu address and data bus, and some control signals that enter their high-imped- ance state. busre q ? bus request (input, active lo w). this input is used by external devices (such as dma cont rollers) to request access to the system bus. this request dema nds a higher priority than nmi and is always recognized at the end of the current machine cycl e. this signal stops the cpu from executing further instruc- tions and places address and data buses, and ot her control signals, in to the high-impedance state. cka0, cka1? asynchronous clock 0 and 1 (bidirectional, active high). when in output mode, these pins are the transmit and receive clock outputs from the asci baud rate generators. when in input mode, th ese pins serve as the external clock inputs for the asci baud rate generators. cka0 is multiplexed with dreq0 , and cka1 is multiplexed with tend0 . cks? serial clock (bidirectional, active high ). this line is the clock for the csio channel. clock? system clock (output, active high). the output is used as a reference clock for the mpu and the external system. the frequency of this output is equal to one-half that of the crystal or input clock frequency. cts0 ?cts 1 ? clear to send 0 and 1 (inputs, active low). these lines are modem control signals for the asci channels. cts1 is multiplexed with rxs . d0?d7? data bus (bidirectional, active high, 3-state). d0?d7 constitute an 8-bit bidirectional data bus, used for the transfer of information to and from i/o and memory devices. the data bus enters the high-impedance state during reset and external bus acknowledge cycles. dcd0? data carrier detect 0 (input, active lo w). a programmable modem control signal for asci channel 0. dreq0, dreq1. dma request 0 and 1 (input, active low). dreq is used to request a dma transfer from one of the on-chip dma channels. the dma channels monitor these inputs to determine when an external device is ready for a read or write operation. these inputs can be programmed to be either level or edge sensed. dreq0 is multiplexed with cka0 . e? enable clock (output, active high). synchronous machine cycle clock output during bus transactions. extal? external clock crystal (input, active hi gh). crystal oscillator connections. an external clock can be input to th e z80180 on this pin when a crys tal is not used. this input is schmitt-triggered. hal t ? halt/sleep (output, active low). this output is asserted after the cpu executes either the halt or sleep instruction, and is waiting for either nonmaskable or maskable
z80180 microprocessor unit 10 ps014004-1106 overview interrupt before operation resum es. it is also used with the m1 and st signals to decode status of the cpu machine cycle. int 0 ? maskable interrupt request 0 (input, active low). this signal is generated by exter- nal i/o devices. the cpu honors these requests at the end of the current instruction cycle as long as the nmi and busreq signals are inactive. the cpu acknowledges this interrupt request with an interrupt acknowledge cycle. during this cycle, both the m1 and iorq signals become active. int1 , int 2 ? maskable interrupt request 1 and 2 (inpu ts, active low). this signal is gener- ated by external i/o devices. the cpu hono rs these requests at th e end of the current instruction cycle as long as the nmi , busreq , and int0 signals are inactive. the cpu acknowledges these requests w ith an interrupt ac knowledge cycle. unlike the acknowledg- ment for int0 , during this cycle neither the m1 or iorq signals become active. ior q ? i/o request (output, active low, 3-state). iorq indicates that the address bus con- tains a valid i/o address for an i/o read or i/o write operation. iorq is also generated, along with m1 , during the acknowledgment of the int0 input signal to indicate that an inter- rupt response vector can be placed onto the data bus. this signal is analogous to the ioe sig- nal of the z64180. m 1 ? machine cycle 1 (output, ac tive low). together with mreq , m1 indicates that the cur- rent cycle is the opcode fetch cycle of and instruction execu tion. together with iorq , m1 indicates that the current cycle is for an interrupt acknowledge. it is also used with the halt and st signal to decode status of the cpu machin e cycle. this signal is analogous to the lir signal of the z64180. mre q ? memory request (output, active low, 3-state). mreq indicates that the address bus holds a valid address for a memory read or memory write operation. this signal is analogous to the me signal of z64180. nm i ? nonmaskable interrupt (input, negative edge triggered). nmi demands a higher prior- ity than int and is always recognized at the end of an instruction, regardless of the state of the interrupt enable flip-flops. this signal forces cpu execution to continue at location 0066h . r d ? opcode reinitialized (outpu t, active low, 3-state). rd indicated that the cpu wants to read data from memory or an i/o device. the addressed i/o or memory device must use this signal to gate data onto the cpu data bus. rfs h ? refresh (output, active low). together with mreq , rfsh indicates that the current cpu machine cycle and the contents of the addr ess bus must be used for refresh of dynamic memories. the low order 8 bits of the address bus ( a7?a10 ) contain the refresh address. this signal is analogous to the r ef signal of the z64180. rts 0 ? request to send 0 (output, active low). a programmable modem control signal for asci channel 0. rxa0, rxa1? receive data 0 and 1 (input, active high ). these signals are the receive data to the asci channels.
z80180 microprocessor unit 11 ps014004-1106 overview rxs? clocked serial receive data (input, active hi gh). this line is the receiver data for the csio channel. rxs is multiplexed with the cts1 signal for asci channel 1. st? status (output, active high). this signal is used with the m1 and halt output to decode the status of the cpu machine cycle. tend0, tend1? transfer end 0 and 1 (outputs, active low). this output is asserted active during the most recent write cycle of a dma operation. it is used to indica te the end of the block transfer. tend0 is multiplexed with cka1 . test? test (output, not in dip version). this pin is for test and must be left open. tout? timer out (output, active high). t out is the pulse output from prt channel 1. this line is multiplexed with a18 of the address bus. txa0, txa1? transmit data 0 and 1 (outputs, activ e high). these signals are the transmit- ted data from the asci channels . transmitted data changes are with respect to the falling edge of the transmit clock. txs? clocked serial transmit data (output, activ e high). this line is the transmitted data from the csio channel. wait? wait (input, active low). wait indicated to the mpu that the addressed memory or i/o devices are not ready for a data transfer. this input is sampled on the falling edge of t2 (and subsequent wait states). if the input is sa mpled low, then the ad ditional wait states are inserted until the wait input is sampled high, at which time execution continues. wr? write (output, active low, 3-state). wr indicated that the cpu data bus holds valid data to be stored at the addressed i/o or memory location. xtal? crystal (input, active high). crystal oscilla tor connection. this pin must be left open if an external clock is used instead of a crystal. the oscillator input is not a ttl level table 3. status summary st halt m1 operation 0 1 0 cpu operation (1st opcode fetch) 1 1 0 cpu operation (2nd opcode and 3rd opcode fetch) 1 1 1 cpu operation (mc ex cept for opcode fetch) 0x1dma operation 000halt mode 1 0 1 sleep mode (including system stop mode) notes: x = reserved. mc = machine cycle.
z80180 microprocessor unit 12 ps014004-1106 overview (see dc characteristics on page 21). several pins are used for different conditions, depending on the circumstance. multiplexed pin descriptions table 4. multiplexed pin descriptions pin description a18/t out during reset, this pin is initialized as a18 pin. if either toc1 or toc0 bit of the timer control regi ster (tcr) is set to 1, t out function is selected. if toc1 and toc0 are clea red to 0, a18 function is selected. cka0/dreq0 during reset, this pin is initializ ed as cka0 pin. if either dm1 or sm1 in dma mode register (dmode) is set to 1, dreq0 function is always selected. cka1/tend0 during reset, this pin is initialized as cka1 pin. if cka1d bit in asci control register ch1 (cntla1) is set to 1, tend0 function is selected. if cka1d bit is set to 0, cka1 function is selected. rxs/cts1 during reset, this pin is initia lized as rxs pin. if cts1e bit in asci status register ch1 (stat1) is set to 1, cts1 function is selected. if cts1e bit is set to 0, rxs function is selected.
z80180 microprocessor unit 13 ps014004-1106 architecture architecture the z180 ? combines a high-performance cpu core with a variety of system and i/o resources useful in a broad rang e of applications. the cpu core consists of five functional blocks: clock generator, bus state controller, interrupt controller, memory management unit (mmu), and the central processing unit (cpu). the integrated i/o resources make up the remaining four functio n blocks: direct memory access (dma) control (2 channels), asynchronous serial communic ation interface (asci) 2 channels, programma- ble reload timers (prt) 2 channels, and a clock serial i/o (csio) channel. clock generator? generates system clock from an external crystal or clock input. the external clock is divided by two or one and pr ovided to both internal and external devices. bus state controller? this logic performs all of the status and bus control activity associated with both the cpu an d some on-chip peripherals. included are wait-state timing, reset cycles, dram refresh, and dma bus exchanges. interrupt controller? this logic monitors and prioriti zes the variety of internal and external interrupts and traps to provide the correct responses from the cpu. to maintain compatibility with the z80 ? cpu, three different interrupts modes are supported. memory management unit? the mmu allows you to map th e memory used by the cpu (logically only 64 kb) into the 1-mb addressing range supported by the z80180. the orga- nization of the mmu object co de allows maintenance comp atibility with the z80 cpu, while offering access to an extended memory sp ace. this organization is achieved by using an effective common area-banked area scheme. central processing unit? the cpu is microcoded to provide a core that is object-code compatible with the z80 cpu. it also provides a superset of the z80 instruction set, includ- ing 8-bit multiply. the core is m odified to allow many of the in structions to execute in fewer clock cycles. dma controller? the dma controller provides high sp eed transfers between memory and i/o devices. transfer operations supported are memory-to-memory, memory to/from i/o, and i/o-to-i/o. transfer modes supported are re quest, burst, and cycle steal. dma transfers can access the full 1 mb address range with a bl ock length up to 64 kb, and can cross over 64k boundaries. asynchronous serial communication interface (asc)? the asci logic provides two individual full-duplex uarts. each channel in cludes a programmable baud rate generator and modem control signals. the asci channels also support a multiprocessor communication format as well as break detection and generation. programmable reload timers (prt)? this logic consists of tw o separate channels, each containing a 16-bit counter (timer) and count re load register. the time base for the counters is derived from the system clock (divided by 20) before reaching the counter. prt channel 1 provides an optional output to allow for waveform generation.
z80180 microprocessor unit 14 ps014004-1106 architecture figure 5. timer initialization, count down, and reload timing figure 6. time r data register clocked serial i/o (csio). the csio channel provides a half-duplex serial transmitter and receiver. this channel can be used for simple high-speed data connection to another micro- processor or microcomputer. trdr is used for both csio transmission and reception. the system design must ensure th at the constraints of half-duplex operation are met. transmit and receive operations cannot occur simultaneously. for example, if a csio transmission is attempted while the csio is receiving data, a csio does not work. trdr is not buffered. attempting to perform a csio transmit while the previous transmit data is still being shifted out causes the shift data to be immediately ffffh 0004h 0003h 0002h 0001h 0000h 0003h 0002h 0001h 0000h 0003h timer data register write (0004h) timer data register timer reload register tde flag tif flag reset 20 f 20 f 20 f 20 f 20 f 20 f 20 f 20 f 20 f 0 < t < 20 f timer reload register write (0003h) ffffh 0003h reload reload write a 1 to tde timer data register read timer control requestor read timer data reg. = 0001h timer data reg. = 0000h t out f note:
z80180 microprocessor unit 15 ps014004-1106 architecture updated, corrupting th e transmit operation in progress. reading trdr while a transmit or receive is in progress must be avoided. figure 7. csio block diagram operation modes z80 ? versus 64180 compatibility the z80180 is descended from two different ance stor processors, zilog's original z80 and the hitachi 64180. the operating mode control register (omcr), illustrated in figure 8 , can be programmed to select between certain z80 and 64180 differences. . figure 8. operating control register (omcr: i/o address = 3eh) m1e (m1 enable)? this bit controls the m1 output and is set to a 1 during reset . when m1e = 1 , the m1 output is asserted low during the opcode fetch cycle, the int0 acknowledge cycle, and the first machine cycle of the nmi acknowledge. internal address/data bus csio transmit/receive data register: trdr (8) csio control register: cntr (8) baud rate generator txs rxs cks interrupt request d7 reserved d6 d5 ? ioc (r/w) m1te (w) m1e (r/w) ? ?? ?
z80180 microprocessor unit 16 ps014004-1106 architecture on the z80180, this choice makes the processor fetch a reti instruction one time only, and when fetching a reti from zero-wait-state memory uses three clock machine cycles, which are not fully z80-timing compatible but are compatible with the on-chip ctcs. when m1e = 0 , the processor does not drive m1 low during instruction fetch cycles. after fetching a reti instruction one time only, with normal timing, the processor goes back and refetches the instruction using fully z80- compatible cycles th at include driving m1 low. some external z80 peripherals may require properly decoded reti instructions. figure 9 illustrates the reti sequence when m1e = 0 . figure 9. reti instruction sequence with mie = 0 m1te (m1 temporary enable)? this bit controls the temporary assertion of the m1 signal. it is always read back as a 1 and is set to 1 during reset . when m1e is set to 0 to accommodate certain external z80 peripheral(s), those same device(s) may require a pulse on m1 after progra mming certain of their registers to complete the function being programmed. for example, when a control word is written to the z80 pio to enable interrupts, no enable actually takes place until the pio identifies an active m1 signal. when m1te = 1 , there is no change in the operation of the m1 signal and m1e controls its function. when m1te = 0 , the m1 output is asserted during the next opcode fetch cycle regardless of the state programmed into the m1e bit. this instance is only momentary (one time only) and you are not required to preprogram a 1 to disable the function (see figure 10 ). t 1 t 2 t 3 t 1 t 2 t 3 t i t i t i t 1 t 2 t 3 t 1 t 2 t 3 t i t i a 0 ?a 18 (a 19 ) d 0 ?d 7 pc pc+1 pc pc+1 edh 4dh edh 4dh mreq m1 rd st
z80180 microprocessor unit 17 ps014004-1106 architecture figure 10. m1 temporary enable timing ioc? this bit controls the timing of the iorq and rd signals. it is set to 1 by reset . when ioc = 1 , the iorq and rd signals function the same as the z64180 ( figure 11 ). figure 11. i/o read and write cycles with ioc = 1 when ioc = 0 , the timing of the iorq and rd signals match the timing of the z80. the iorq and rd signals go active as a result of the rising edge of t2 (see figure 12 ). figure 12. i/o read and write cycles with ioc = 0 t 1 t 2 t 3 t 1 t 2 t 3 f wr m1 opcode fetch write into omcr t 1 t 2 t w t 3 iorq rd wr t 1 t 2 t w t 3 iorq rd wr
z80180 microprocessor unit 18 ps014004-1106 architecture halt and low-power operating modes? the z80180 can operate in five modes with respect to activity and power consumption: ? normal operation ? halt mode ? iostop mode ? sleep mode ? system stop mode normal operation? the z80180 processor is fetching an d running a program. all enabled functions and portions of the device are active, and the halt pin is high. halt mode? this mode is entered by the halt instruction. thereafter, the z80180 processor continually fetches th e following opcode but does not execute it, and drives the halt , st and m1 pins all low. the oscillator and phi pin remain active, interrupts and bus granting to external masters, and dram re fresh can occur and all on-chip i/o devices continue to operate incl uding the dm a channels. the z80180 leaves halt mode in response to a low on reset , on to an interrupt from an enabled on-chip source, an external request on nmi , or an enabled external request on int0 , int1 , or int2 . in case of an interrupt, the return address is the instruction following the halt instruction; at that point the prog ram can either branch back to the halt instruction to wait for another interrupt, or can examine the new state of the system/application and respond appropriately. figure 13. halt timing halt opcode fetch cycle halt mode t 2 t 3 t 1 t 2 t 3 t 1 t 2 int i , nmi a 0 ?a 19 halt m1 mreq rd interrupt acknowledge cycle halt opcode address halt opcode address + 1
z80180 microprocessor unit 19 ps014004-1106 architecture sleep mode? enter sleep mode by keeping the iostop bit ( icr5 ) bits 3 and 6 of the cpu control register ( ccr3 , ccr6 ) all zero and executing the sleep instruction. the oscillator and phi output continue operating, but ar e blocked from the cpu core and dma channels to reduce power consumption. dram refresh stops but interrupts and granting to external master can occur. except wh en the bus is granted to an external master, a19?0 and all control signals except halt are maintained high. halt is low. i/o opera- tions continue as before the sleep instruction, except for the dma channels. the z80180 leaves sleep mode in response to a low on reset , an interrupt request from an on-chip source, an external request on nmi , or an external request on int0 , int1 , or int2 . if an interrupt source is individually di sabled, it cannot bring the z80180 out of sleep mode. if an interrupt source is individually en abled, and the ief bit is 1 so that interrupts are globally enabled (by an ei instruction), the highest priority active interrupt occurs, with the return address being the instruction after the sleep instruction. if an interrupt source is indi- vidually enabled, but the ief bit is 0 so that interrupts are globally disabled (by a di instruc- tion), the z80180 leaves sleep mode by simply executing th e following instruction(s). this provides a technique for synchronization with high- sp eed external events without incurring the latency imposed by an interrupt response sequence. figure 14 displays the timing for exiting sleep mode due to an interrupt request. the z80180 takes about 1.5 clocks to restart. figure 14. sleep timing iostop mode? iostop mode is entered by setting the iostop bit of the i/o control register ( icr ) to 1 . in this case, on-chip i/o ( asci , csio , prt ) stops operating. however, the cpu continues to operate. recovery from iostop mode is by resetting the iostop bit in icr to 0 . system stop mode? system stop mode is the combination of sleep and iostop modes. system stop mode is entered by setting the iostop bit in icr to 1 followed by note: sleep 2nd opcode sleep mode t 2 t 3 t 1 t 2 t s t s t 1 int i , nmi a 0 ?a 19 halt m1 opcode fetch or interrupt acknowledge cycle sleep 2nd opcode address fffffh fetch cycle t 2 t 3
z80180 microprocessor unit 20 ps014004-1106 architecture execution of the sleep instruction. in this mode, on-c hip i/o and cpu stop operating, reducing power consumption, but the phi output continues to operate. recovery from sys- tem stop mode is the same as recovery from sleep mode except that internal i/o sources (disabled by iostop ) cannot generate a recovery interrupt. standard test conditions the dc characteristics section applie s to the following standard test conditions, unless otherwise noted. all voltages are referenced to gnd (0 v). positive current flow s in to the referenced pin. all ac parameters assume a load capacitance of 100 pf. add 10 ns delay for each 50 pf increase in load up to a maximum of 200 pf fo r the data bus and 100 pf for the address and control lines. ac timing measurements are referenced to 1.5 volts (except for clock , which is referenced to the 10% and 90% poin ts). the ordering information section lists temperature ranges and product numbers. package drawings are in the package information section (see figure 15 ). figure 15. ac load capacitance parameters absolute maximum ratings permanent lsi damage occurs if maximum ratings listed in table 5 are exceeded. table 5. absolute maximum ratings item symbol value unit supply voltage v cc ?0.3 ~ +7.0 v input voltage v in ?0.3 ~ v cc +0.3 v operating temperature t opr 0 ~ 70 c +5 v from output 100 pf under test 250 a 2.1k
z80180 microprocessor unit 21 ps014004-1106 architecture normal operation must be under reco mmended operating conditions. if these conditions are exceeded, it affects reliability of lsi. dc characteristics table 6 lists the dc characteristics of z80180 ? mpu. extended temperature t ext ?40 ~ 85 c storage temperature t stg ?55 ~ +150 c table 6. dc characteristics symbol item condition min typ max unit v ih1 input h voltage reset , extal, nmi v cc ?0.6 ? v cc +0.3 v v ih2 input h voltage except reset , extal, nmi 2.0 ? v cc +0.3 v v il1 input l voltage reset , extal, nmi ?0.3 ? 0.6 v v il2 input l voltage except reset , extal, nmi ?0.3 ? 0.8 v v oh outputs h voltage all outputs i oh = ?200 a 2.4 ? ? v i oh = ?20 a v cc ?1.2 ? ? v ol outputs l voltage all outputs i ol = ?2.2 ma ? ? 0.45 v i il input leakage current all inputs except xtal, extal v in = 0.5 ~ v cc ?0.5 ??1.0a i tl three state leakage current v in = 0.5 ~ v cc ?0.5 ??1.0a i cc* power dissipation* (normal operation) f = 6 mhz ? 15 40 ma f = 8 mhz ? 20 50 f = 10 mhz** ? 25 60 power dissipation* (system stop mode) f = 6 mhz ? 3.8 12.5 f = 8 mhz ? 5 15 f = 10 mhz** ? 6.3 17.5 table 5. absolute maximum ratings(continued) item symbol value unit note:
z80180 microprocessor unit 22 ps014004-1106 architecture ac characteristics table 7 , table 8 , and table 9 provide ac characteristics for the z80180-6, z80180-8, and z80180-10, respectively. v cc = 5 v + 10%, v ss = 0 v, ta ? 0 c to +70 c, unless otherwise noted. c p pin capacitance v in v in = 0v, = 1 mhz t a = 25 c ??12pf note: *v ihmin = v cc ?1.0 v, v ilmax = 0.8 v (all output terminals are at no load); v cc = 5.0 v. **v cc = 5 v + 10%, v ss = 0 v over specified temperatur e range, unless otherwise noted table 7. z80180-6 ac characteristics no symbol item z80180-6 unit min max 1t cyc clock cycle time 162 2000 ns 2t chw clock h pulse width 65 ? ns 3t clw clock l pulse width 65 ? ns 4t cf clock fall time ? 15 ns 5t cr clock rise time ? 15 ns 6t ad ?rise to address valid delay ? 90 ns 7t as address valid to mreq fall or iorq fall) 30 ? ns 8t med1 ? fall to mreq fall delay ? 60 ns 9t rdd1 ? fall to rd fall delay ioc = 1 ? 60 ns ? rise to rd rise delay ioc = 0 ? 65 10 t m1d1 ? rise to m1 fall delay ? 80 ns 11 t ah address hold time from (mreq , ioreq , rd , wr ) 35 ? ns 12 t med2 ? fall to mreq rise delay ? 60 ns 13 t rdd2 ? fall to rd rise delay ? 60 ns 14 t m1d2 ? rise to m1 rise delay ? 80 ns 15 t drs data read set-up time 40 ? ns 16 t drh data read hold time 0 ? ns 17 t std1 ? fall to st fall delay ? 90 ns 18 t std2 ? fall to st rise delay ? 90 ns 19 t ws wait set-up time to ? fall 40 ? ns table 6. dc characteristics (continued) symbol item condition min typ max unit
z80180 microprocessor unit 23 ps014004-1106 architecture 20 t wh wait hold time from ? fall 40 ? ns 21 t wdz ? rise to data float delay ? 95 ns 22 t wrd1 ? rise to wr fall delay ? 65 ns 23 t wdd ? fall to write data delay time ? 90 ns 24 t wds write data set-up time to wr fall 40 ? ns 25 t wrd2 ? fall to wr rise delay ? 80 ns 26 t wrp wr pulse width 170 ? ns 26a wr pulse width (i/o write cycle) 332 ? ns 27 t wdh write data hold time from ( wr rise ) 40 ? 28 t iod1 ? fall to iorq fall delay ioc = 1 ? 60 ns ? rise to iorq fall delay ioc = 1 ? 65 29 t iod2 ? fall to iorq rise delay ? 60 ns 30 t iod3 m1 fall to iorq fall delay 340 ? ns 31 t ints int set-up time to ? fall 40 ? ns 32 t ints int hold time from ? fall 40 ? ns 33 t nmiw nmi pulse width 120 ? ns 34 t brs busreq set-up time to ? fall 40 ? ns 35 t brh busreq hold time from ? fall 40 ? ns 36 t bad1 ? rise to busack fall delay ? 95 ns 37 t bad2 ? fall to busack rise delay ? 90 ns 38 t bzd ? rise to bus floating delay time ? 125 ns 39 t mewh mreq pulse width (high) 110 ? ns 40 t mewl mreq pulse width (low) 125 ? ns 41 t rfd1 ? rise to rfsh fall delay ? 90 ns 42 t rfd2 ? rise to rfsh rise delay ? 90 ns 43 t had1 ? rise to halt fall delay ? 90 ns 44 t had2 ? rise to halt rise delay ? 90 ns 45 t drqs /dreqi set-up time to ? rise 40 ? ns 46 t drqh /dreqi hold time from ? rise 40 ? ns 47 t ted1 ? fall to tendi fall delay ? 70 ns 48 t ted2 ? fall to tendi rise delay ? 70 ns 49 t ed1 ? rise to e rise delay ? 95 ns 50 t ed2 ? fall or rise to e fall delay ? 95 ns 51 p weh e pulse width (high) 75 ? ns 52 p wel e pulse width (low) 180 ? ns 53 t er enable rise time ? 20 ns 54 t ef enable fall time ? 20 ns table 7. z80180-6 ac characteristics (continued) no symbol item z80180-6 unit min max
z80180 microprocessor unit 24 ps014004-1106 architecture 55 t tod ? fall to timer output delay ? 300 ns 56 t stdi csio transmit data dela y time (internal clock operation) ? 200 ns 57 t stde csio transmit data dela y time (external clock operation) ? 7.5tcyc +300 ns 58 t srsi csio receive data set-up time (internal clock operation) 1? tcyc 59 t srhi csio receive data hold time (internal clock operation) 1? tcyc 60 t srse csio receive data set-up time (external clock operation) 1? tcyc 61 t srhe csio receive data hold time (external clock operation) 1? tcyc 62 t res reset set-up time to ? fall 120 ? ns 63 t reh reset hold time from ? fall 80 ? ns 64 t osc oscillator stabilization time ? 20 ns 65 t exr external clock rise time (extal) ? 25 ns 66 t exf external clock fall time (extal) ? 25 ns 67 t rr reset rise time ? 50 ns 68 t rf reset fall time ? 50 ns 69 t ir input rise time (e xcept extal, reset )?100ns 70 t if input fall time (except extal, reset )?100ns table 8. z80180-8 ac characteristics no symbol item z80180-8 unit min max 1t cyc clock cycle time 125 2000 ns 2t chw clock h pulse width 50 ? ns 3t clw clock l pulse width 50 ? ns 4t cf clock fall time ? 15 ns 5t cr clock rise time ? 15 ns 6t ad ?rise to address valid delay ? 80 ns 7t as address valid to mreq fall or iorq fall) 20 ? ns table 7. z80180-6 ac characteristics (continued) no symbol item z80180-6 unit min max
z80180 microprocessor unit 25 ps014004-1106 architecture 8t med1 ? fall to mreq fall delay ? 50 ns 9t rdd1 ? fall to rd fall delay ioc = 1 ? 50 ns ? rise to rd rise delay ioc = 0 ? 60 10 t m1d1 ? rise to m1 fall delay ? 70 ns 11 t ah address hold time from (mreq , ioreq , rd , wr ) 20 ? ns 12 t med2 ? fall to mreq rise delay ? 50 ns 13 t rdd2 ? fall to rd rise delay ? 50 ns 14 t m1d2 ? rise to m1 rise delay ? 70* ns 15 t drs data read set-up time 30 ? ns 16 t drh data read hold time 0 ? ns 17 t std1 ? fall to st fall delay ? 70 ns 18 t std2 ? fall to st rise delay ? 70 ns 19 t ws wait set-up time to ? fall 40 ? ns 20 t wh wait hold time from ? fall 40 ? ns 21 t wdz ? rise to data float delay ? 70 ns 22 t wrd1 ? rise to wr fall delay ? 60 ns 23 t wdd ? fall to write data delay time ? 80 ns 24 t wds write data set-up time to wr fall 20 ? ns 25 t wrd2 ? fall to wr rise delay ? 60 ns 26 t wrp wr pulse width 130 ? ns 26a wr pulse width (i/o write cycle) 255 ? ns 27 t wdh write data hold time from ( wr rise ) 15 ? 28 t iod1 ? fall to iorq fall delay ioc = 1 ? 50 ns ? rise to iorq fall delay ioc = 1 ? 60 29 t iod2 ? fall to iorq rise delay ? 50 ns 30 t iod3 m1 fall to iorq fall delay 250 ? ns 31 t ints int set-up time to ? fall 40 ? ns table 8. z80180-8 ac characteristics (continued) no symbol item z80180-8 unit min max
z80180 microprocessor unit 26 ps014004-1106 architecture 32 t ints int hold time from ? fall 40 ? ns 33 t nmiw nmi pulse width 100 ? ns 34 t brs busreq set-up time to ? fall 40 ? ns 35 t brh busreq hold time from ? fall 40 ns 36 t bad1 ? rise to busack fall delay ? 70 ns 37 t bad2 ? fall to busack rise delay ? 70 ns 38 t bzd ? rise to bus floating delay time ? 90 ns 39 t mewh mreq pulse width (high) 90 ? ns 40 t mewl mreq pulse width (low) 100 ? ns 41 t rfd1 ? rise to rfsh fall delay ? 80 ns 42 t rfd2 ? rise to rfsh rise delay ? 80 ns 43 t had1 ? rise to halt fall delay ? 80 ns 44 t had2 ? rise to halt rise delay ? 80 ns 45 t drqs /dreqi set-up time to ? rise 40 ? ns 46 t drqh /dreqi hold time from ? rise 40 ? ns 47 t ted1 ? fall to tendi fall delay ? 60 ns 48 t ted2 ? fall to tendi rise delay ? 60 ns 49 t ed1 ? rise to e rise delay ? 70 ns 50 t ed2 ? fall or rise to e fall delay ? 70 ns 51 p weh e pulse width (high) 65 ? ns 52 p wel e pulse width (low) 130 ? ns 53 t er enable rise time ? 20 ns 54 t ef enable fall time ? 20 ns 55 t tod ? fall to timer output delay ? 200 ns 56 t stdi csio transmit data dela y time (internal clock operation) ?200ns 57 t stde csio transmit data dela y time (external clock operation) ? 7.5tcy c +200 ns table 8. z80180-8 ac characteristics (continued) no symbol item z80180-8 unit min max
z80180 microprocessor unit 27 ps014004-1106 architecture 58 t srsi csio receive data set-up time (internal clock operation) 1?tcyc 59 t srhi csio receive data hold time (internal clock operation) 1?tcyc 60 t srse csio receive data set-up time (external clock operation) 1?tcyc 61 t srhe csio receive data hold time (external clock operation) 1?tcyc 62 t res reset set-up time to ? fall 100 ? ns 63 t reh reset hold time from ? fall 70 ? ns 64 t osc oscillator stabilization time ? 20 ns 65 t exr external clock rise time (extal) ? 25 ns 66 t exf external clock fall time (extal) ? 25 ns 67 t rr reset rise time ? 50 ns 68 t rf reset fall time ? 50 ns 69 t ir input rise time (e xcept extal, reset )?100ns 70 t if input fall time (except extal, reset )?100ns table 9. z80180-10 ac characteristics no symbol item z80180-10 unit min max 1t cyc clock cycle time 100 2000 ns 2t chw clock h pulse width 40 ? ns 3t clw clock l pulse width 40 ? ns 4t cf clock fall time ? 10 ns 5t cr clock rise time ? 10 ns 6t ad ?rise to address valid delay ? 70 ns 7t as address valid to mreq fall or iorq fall) 10 ? ns table 8. z80180-8 ac characteristics (continued) no symbol item z80180-8 unit min max
z80180 microprocessor unit 28 ps014004-1106 architecture 8t med1 ? fall to mreq fall delay ? 50 ns 9t rdd1 ? fall to rd fall delay ioc = 1 ? 50 ns ? rise to rd rise delay ioc = 0 ? 55 10 t m1d1 ? rise to m1 fall delay ? 60 ns 11 t ah address hold time from (mreq , ioreq , rd , wr ) 10 ? ns 12 t med2 ? fall to mreq rise delay ? 50 ns 13 t rdd2 ? fall to rd rise delay ? 50 ns 14 t m1d2 ? rise to m1 rise delay ? 60 ns 15 t drs data read set-up time 25 ? ns 16 t drh data read hold time 0 ? ns 17 t std1 ? fall to st fall delay ? 60 ns 18 t std2 ? fall to st rise delay ? 60 ns 19 t ws wait set-up time to ? fall 30 ? ns 20 t wh wait hold time from ? fall 30 ? ns 21 t wdz ? rise to data float delay ? 60 ns 22 t wrd1 ? rise to wr fall delay ? 50 ns 23 t wdd ? fall to write data delay time ? 60 ns 24 t wds write data set-up time to wr fall 15 ? ns 25 t wrd2 ? fall to wr rise delay ? 50 ns 26 t wrp wr pulse width 110 ? ns 26a wr pulse width (i/o write cycle) 210 ? ns 27 t wdh write data hold time from ( wr rise ) 10 ? 28 t iod1 ? fall to iorq fall delay ioc = 1 ? 50 ns ? rise to iorq fall delay ioc = 1 ? 55 29 t iod2 ? fall to iorq rise delay ? 50 ns 30 t iod3 m1 fall to iorq fall delay 200 ? ns 31 t ints int set-up time to ? fall 30 ? ns table 9. z80180-10 ac characteristics (continued) no symbol item z80180-10 unit min max
z80180 microprocessor unit 29 ps014004-1106 architecture 32 t ints int hold time from ? fall 30 ? ns 33 t nmiw nmi pulse width 80 ? ns 34 t brs busreq set-up time to ? fall 30 ? ns 35 t brh busreq hold time from ? fall 30 ns 36 t bad1 ? rise to busack fall delay ? 60 ns 37 t bad2 ? fall to busack rise delay ? 60 ns 38 t bzd ? rise to bus floating delay time ? 80 ns 39 t mewh mreq pulse width (high) 70 ? ns 40 t mewl mreq pulse width (low) 80 ? ns 41 t rfd1 ? rise to rfsh fall delay ? 60 ns 42 t rfd2 ? rise to rfsh rise delay ? 60 ns 43 t had1 ? rise to halt fall delay ? 50 ns 44 t had2 ? rise to halt rise delay ? 50 ns 45 t drqs /dreqi set-up time to ? rise 30 ? ns 46 t drqh /dreqi hold time from ? rise 30 ? ns 47 t ted1 ? fall to tendi fall delay ? 50 ns 48 t ted2 ? fall to tendi rise delay ? 50 ns 49 t ed1 ? rise to e rise delay ? 60 ns 50 t ed2 ? fall or rise to e fall delay ? 60 ns 51 p weh e pulse width (high) 55 ? ns 52 p wel e pulse width (low) 110 ? ns 53 t er enable rise time ? 20 ns 54 t ef enable fall time ? 20 ns 55 t tod ? fall to timer output delay ? 150 ns 56 t stdi csio transmit data dela y time (internal clock operation) ? 150 ns 57 t stde csio transmit data dela y time (external clock operation) ? 7.5tcy c +150 ns table 9. z80180-10 ac characteristics (continued) no symbol item z80180-10 unit min max
z80180 microprocessor unit 30 ps014004-1106 architecture timing diagrams z80180 timing signals are displayed in figure 16 through figure 27 . 58 t srsi csio receive data set-up time (internal clock operation) 1?tcyc 59 t srhi csio receive data hold time (internal clock operation) 1?tcyc 60 t srse csio receive data set-up time (external clock operation) 1?tcyc 61 t srhe csio receive data hold time (external clock operation) 1?tcyc 62 t res reset set-up time to ? fall 80 ? ns 63 t reh reset hold time from ? fall 50 ? ns 64 t osc oscillator stabilization time ? tbd ns 65 t exr external clock rise time (extal) ? 25 ns 66 t exf external clock fall time (extal) ? 25 ns 67 t rr reset rise time ? 50 ns 68 t rf reset fall time ? 50 ns 69 t ir input rise time (e xcept extal, reset )?100ns 70 t if input fall time (except extal, reset )?100ns table 9. z80180-10 ac characteristics (continued) no symbol item z80180-10 unit min max
z80180 microprocessor unit 31 ps014004-1106 architecture figure 16. cpu timing (opcode fetch, i/o write, and i/o read cycles) p h i a d d r e s s w a i t m r e q i o r q r d w r m 1 s t d a t a i n d a t a o u t r e s e t 1 1 6 7 6 8 6 2 6 3 6 8 6 7 6 2 6 3 1 5 1 6 1 7 1 0 1 4 9 2 2 1 3 1 1 2 8 7 2 9 7 8 2 0 1 9 1 9 2 0 1 1 1 2 6 9 1 3 2 5 1 1 o p c o d e f e t c h c y c l e t 1 1 2 3 4 5 1 5 1 6 2 1 2 7 1 8 i / o w r i t e c y c l e * i / o r e a d c y c l e * t 2 t w t 3 t 1 t 2 t w t 3 t 1 2 3 2 4 2 6
z80180 microprocessor unit 32 ps014004-1106 architecture figure 17. cpu timing ( int0 acknowledge cycle, refresh cycle) ? inti 31 32 33 40 30 28 15 16 29 39 41 42 34 35 34 35 36 37 38 38 43 44 *3 14 10 nmi mi *1 iorq *1 date in *1 mreq *2 rfsh *2 busreq busack address data mreq , rd wr , iorq halt
z80180 microprocessor unit 33 ps014004-1106 architecture figure 18. cpu timing (ioc = 0) (i/o read cycle, i/o write cycle) cpu timin= 0) (i/o read cycle, i/o write cycle) t 1 t 2 t w t 3 t 1 t 2 t w t 3 address rd iroq wr 28 9 29 28 29 13 22 25 i/o read cycle i/o write cycle cpu timing (ioc=0) i/o read cycle i/o write cycle
z80180 microprocessor unit 34 ps014004-1106 architecture figure 19. dma control signals dma control signals notes: 1. t drqs and t dhqh are specified for the rising edge of clock followed by t 3 . 2. t drqs and t dhqh are specified for the rising edge of clock. 3. dma cycle starts. 4. cpu cycle starts. 47 45 46 48 18 *4 *2 (at level sense) dreqi (at level sense) tendi st ? t 1 t 2 t w t 3 t 1 *3 17 dreqi cpu or dma read/write cycle (only dma write cycle for tendi ) 45 46 *1
z80180 microprocessor unit 35 ps014004-1106 architecture figure 20. e clock timing (mem ory r/w cycle, i/o r/w cycle) figure 21. e clock timing (bus release, sleep, system stop modes e clock timing (bus release, sleep, system stop modes) figure 22. e clock timing (p wel and p weh minimum timing) e clock timing (memory read/write cycle, i/o read/write cycle) e e clock timing (minimum timing example of 49 49 49 15 50 50 50 16 d 0 ?d 7 e (memory read/write) e (i/o read) e (i/o write) ? ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t 1 t 2 t w t w t 3 ph1? e bus release mode sleep mode system stop mode 49 50 50 52 53 49 53 t 2 t 2 t w t 3 t 1 54 49 51 54 50 e example i/o read opcode fetch
z80180 microprocessor unit 36 ps014004-1106 architecture figure 23. timer output timing figure 24. sleep execution cycle timer output timing execution cycle 55 timer data reg.=0000h a 18 /t out 32 44 43 33 a 0 ?a 18 sleep instruction fetch mreq , m1 nmi inti halt ? ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t 1 t 2 t s t s t 3 t 1 t 2 31 rd next opcode fetch ~ ~ ~ ~
z80180 microprocessor unit 37 ps014004-1106 architecture figure 25. csio re ceive/transmit timing figure 26. rise time and fall times asci register description the following sections explain th e various functions of the asci registers. figure 27 displays the asci block diagram. csio receive/transmit timing rise time and fall times 57 56 58 56 11.5t cyc transmit data 59 58 59 11.5t cyc 11t cyc 16.5t cyc 11t cyc 16.5t cyc 57 60 61 60 61 (external clock) transmit data (internal clock) receive data (external clock) receive data (internal clock) csio clock 65 66 v il1 v ih1 extal v il1 v ih1 70 69 input rise time and exter- nal
z80180 microprocessor unit 38 ps014004-1106 architecture figure 27. asci block diagram asci registers asci transmit shift register 0 (tsr0, tsr1)? when the asci transmit shift register ( tsr ) receives data from the asci transmit data register ( tdr ), the data is shifted out to the txa pin. when transmission is complete d, the next byte (if available) is automatically loaded from tdr into tsr and the next transmission starts. if no data is available for transmission, tsr idle s by outputting a contin uous high level. this register is not program accessible. asci transmit data register 0,1 (tdr0, tdr1)? i/o address = 06h, 07h . data written to the asci transmit data register is transferred to the tsr as soon as tsr is empty. data can be written while tsr is shifting out the previous byte of data. the asci transmitter is double buffered. asci block diagram internal address/data bus asci transmit data register ch 0: tdr0 asci transmit shift register* ch 0: tsr0 asci receive data fifo ch 0: rdr0 asci receive shift register* ch 0: rsr0 (8) asci control register a ch 0: cntla0 (8) asci control register b ch 0: cntb0 (8) asci status register ch 0: stat0 (8) asci status fifo ch 0 asci transmit data register ch 1: tdr1 asci transmit shift register* ch 1: tsr1 asci receive data fifo ch 1: rdr1 asci receive shift register* ch 1: rsr1 (8) asci control register a ch 1: cntla1 (8) asci control register b ch 1: cntb1 (8) asci status register ch 1: stat1 (8) asci status fifo ch 1 txa 0 rxa 0 rts 0 cts 0 dcd 0 txa 1 rxa 1 cts 1 asci control baud rate generator 0 baud rate generator 1 cka 0 cka 1 note: *not program interrupt request accessible.
z80180 microprocessor unit 39 ps014004-1106 architecture data can be written into and read from the asci transmit data register. if data is read from the asci transmit data register , the asci data transmit oper ation is not affected by this read operation. asci receive shift register 0,1 (rsr0, rsr1)? this register receives data shifted in on the rxa pin. when full, data is automatically tran sferred to the asci receive data register ( rdr ) if it is empty. if rsr is not empty when the next incomi ng data byte is shifted in, an overrun error occurs. this register is not program accessible. asci receive data fifo 0,1 (rdr0, rdr1)? i/o address = 08h , 09h . the asci receive data register is a read-only register. when a complete incoming data byte is assembled in rsr , it is automatically transferred to the 4 character receive data first-in first-out (fifo) memory. the oldest character in the fifo (if any) can be read from the receive data register ( rdr ). the next incoming data byte can be shifted into rsr while the fifo is full. the asci receiver is well buffered. asci transmit data registers register addresses 06h and 07h hold the asci transmit data for channel 0 and channel 1, respectively. channel 0 mnemonics tdr0 (address 06h) figure 28. asci register channel 0 asci transmit channel 0 ? ? ?? ? ?- ? 76 54 32 1 ?-
z80180 microprocessor unit 40 ps014004-1106 architecture channel 1 mnemonics tdr1 (address (07h) figure 29. asci register channel 1 asci receive registers register addresses 08h and 09h hold the asci receive data for channel 0 and channel 1, respectively. channel 0 mnemonics tsr0 (address (08h) figure 30. asci receive register channel 0 asci receive register channel 0 asci transmit channel 1 ? ? ?? ? ?- ? 76 54 32 1 ?- asci receive data ? ? ?? ? ?? ? 76 54 32 1
z80180 microprocessor unit 41 ps014004-1106 architecture channel 1 mnemonics tsr1 (address (09h) figure 31. asci receive register channel 1r asci channel control register a figure 32. asci channe l control register a mpe: multi-processor mode enable (bit 7)? the asci features a multiprocessor communication mode that u tilizes an extra data bit for selective communication when a number of processors share a comm on serial bus. multiprocessor data format is selected when the mp bit in cntlb is set to 1 . if multiprocessor mode is not selected ( mp bit in cntlb = 0 ), mpe exhibits no effect. if multip rocessor mode is selected, mpe enables or disables the wa ke-up feature as follows. if mbe is set to 1 , only received bytes in which the mpb (multiprocessor bit) = 1 can affect the rdrf and error flags. effectively, other bytes (with mpb = 0 ) are ignored by the asci . if asci receive register channel 1r asci channel control register a asci receive data ? ? ?? ? ?? ? 76 54 32 1 bit mpe re r/w r/w r/w te 76 5 4 3 21 0 rts 0 mpbr/ mod2 mod1 mod0 r/w r/w asci control register a 0 (cntla0: i/o address = 00h) r/w r/w r/w efr bit mpe re r/w r/w r/w te 76 5 4 3 21 0 __ mod2 mod1 mod0 r/w r/w asci control register a 1 (cntla1: i/o address = 01h) r/w r/w r/w mpbr/ efr
z80180 microprocessor unit 42 ps014004-1106 architecture mpe is reset to 0 , all bytes, regardless of the state of the mpb data bit, affect the redr and error flags. mpe is cleared to 0 during reset . re: receiver enable (bit 6)? when re is set to 1 , the asci transmitter is enabled. when te is reset to 0 , the transmitter is disables and any transmit operation in progress is interrupted. however, the tdre flag is not reset and the previous contents of tdre are held. te is cleared to 0 in iostop mode during reset . te: transmitter enable (bit 5)? when te is set to 1 , the asci receiver is enabled. when te is reset to 0 , the transmitter is disabled and any transmit operation in progress is interrupted. however, the tdre flag is not reset and the previous contents of tdre are held. te is cleared to 0 in iostop mode during reset . rts0: request to send channel 0 (bit 4 in cntla0 only)? if bit 4 of the system configuration register is 0 , the rts0 /txs pin features the rts0 function. rts0 allows the asci to control ( start/stop ) another communication devices transmission (for example, by connecting to that device?s cts input). rts0 is essentially a 1 bit output port, having no side effects on other asci registers or flags. bit 4 in cntla1 is not used. mpbr/efr: multiprocessor bit rece ive/error flag reset (bit 3)? when multiprocessor mode is enabled ( mp in cntlb = 1 ), mpbr , when read, contains the value of the mpb bit for the most recent receive op eration. when written to 0 , the efr function is selected to reset all error flags ( ovrn , fe , pe and brk in the asext register) to 0 . mpbr/efr is undefined during reset . mod2, 1, 0: asci data format mode 2, 1, 0 (bits 2?0)? these bits program the asci data format as listed in table 10 . the data formats available b ased on all combinations of mod2 , mod1 , and mod0 are indicated in table 11 . table 10. asci data formats mode 2, 1, 0 bit description mod2 = 0 0 7 bit data mod2 = 1 1 8 bit data mod1 = 0 0 no parity mod1 = 1 1 parity enabled mod0 = 0 0 1 stop bit mod0 = 1 1 2 stop bits
z80180 microprocessor unit 43 ps014004-1106 architecture asci channel control register b figure 33. asci channe l control register b mpbt: multiprocessor bi t transmit (bit 7)? when multiprocessor co mmunication format is selected ( mp bit = 1 ), mpbt is used to specify the mpb data bit for transmission. if mpbt = 1 , then mpb = 1 is transmitted. if mpbt = 0 , then mpb = 0 is transmitted. mpbt state is undefined during and after reset . mp: multiprocessor mode (bit 6)? when mp is set to 1 , the data format is configured for multiprocessor mode based on the mod2 (number of data bits) and mod0 (number of stop bits) bits in cntla . the format is as follows. start bit + 7 or 8 data bits + mpb bit + 1 or 2 stop bits multiprocessor ( mp=1 ) format does not feature any provision for parity. if mp = 0 , the data format is based on mod0 , mod1 , mod2 , and may include parity. the mp bit is cleared to 0 during reset . cts /ps: clear to send/prescale (bit 5)? if bit 5 of the system configuration register is 0 , the cts0 / rxs pin features the cts0 function, and the state of the pin can be read in bit 5 table 11. data formats mod2 mod1 mod0 data format 0 0 0 start + 7 bit data + 1 stop 0 0 1 start + 7 bit data + 2 stop 0 1 0 start + 7 bit data + parity + 1 stop 0 1 1 start + 7 bit data + parity + 2 stop 1 0 0 start + 8 bit data + 1 stop 1 0 1 start + 8 bit data + 2 stop 1 1 0 start + 8 bit data + parity + 1 stop 1 1 1 start + 8 bit data + parity + 2 stop asci channel control register b bit mpbt mp r/w r/w r/w cts / 76 5 4 3 21 0 peo dr ss2 ss1 ss0 r/w r/w asci control register b 1 (cntlb1: i/o address = 03h) r/w r/w r/w asci control register b 0 (cntlb0: i/o address = 02h) ps
z80180 microprocessor unit 44 ps014004-1106 architecture of cntlb0 in a real-time, positive-logic fashion ( high = 1 , low = 0). if bit 5 in the system configuration register is 0 to auto-enable cts0 , and the pin is negated (high), the tdre bit is inhibited (forced to 0 ). bit 5 of cntlb1 reads back as 0 . if the ss2?0 bits in this register are not 111 , and the brg mode bit in the asext register is 0 , then writing to this bit sets the prescale (ps) control. under these ci rcumstances, a 0 indi- cates a divide-by-10 prescale function, while a 1 indicates divide-by-30. the bit resets to 0 . peo: parity even odd (bit 4)? peo selects oven or odd parity. peo does not affect the enabling/disabling of parity ( mod1 bit of cntla ). if peo is cleared to 0 , even parity is selected. if peo is set to 1 , odd parity is selected. peo is cleared to 0 during reset . dr: divide ratio (bit 3)? if the x1 bit in the asext register is 0 , this bit specifies the divider used to obtain baud rate from the data sampling clock. if dr is reset to 0 , divide- by- 16 is used, while if dr is set to 1 , divide-by-64 is used. dr is cleared to 0 during reset . ss2,1,0: source/speed select 2,1,0 (bits 2?0)? if these bits are 111 , as they are after reset , the cka pin is used as a clock input, and is divided by 1, 16, or 64 depending on the dr bit and the x1 bit in the asext register. if these bits are not 111 and the brg mode bit is asext is 0 , these bits specify a power-of- two divider for the phi clock as indicated in table 12 . setting or leaving these bits as 111 makes sense for a channel only when its cka pin is selected for the cka function. ckao/cks features the ckao function when bit 4 of the system configuration register is 0 . dcd0 /cka1 features the cka1 function when bit 0 of the interrupt edge register is 1 . table 12. divide ratio ss2 ss1 ss0 divide ratio 000 1 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 external clock
z80180 microprocessor unit 45 ps014004-1106 architecture asci status register 0, 1 (stat0, 1) each channel status register allows interroga tion of asci communication, error and modem control signal status, and enablin g or disabling of asci interrupts. figure 34. asci status registers rdrf: receive data register full (bit 7)? rdrf is set to 1 when an incoming data byte is loaded into an empty rxfifo . if a framing or parity error occurs, rdrf is still set and the receive data (which generated the error) is sti ll loaded into the fifo. rdrf is cleared to 0 by reading rdr and most recent character in the fifo from iostop mode, during reset and for asci0 if the dcd0 input is auto-enabled and is negated (high). ovrn: overrun error (bit 6)? an overrun condition occurs when the receiver finishes assembling a character, but the rxfifo is full so that there is no room for the character. however, this status bit is not set until the mo st recent character received before the overrun becomes the oldest byte in the fifo. this bit is cleared when software writes a 1 to the efr bit in the cntla register, and also by reset , in iostop mode, and for asci0 if the dcd0 pin is auto enabled an d is negated (high). when an overrun occurs, the receiver does not place the character in the shift register into the fifo, nor any subsequent characters, until th e last good character comes to the top of the fifo so that ovrn is set, and software then writes a 1 to efr to clear it. pe: parity error (bit 5)? a parity error is detected when parity checking is enabled by the mod1 bit in the cnt1la register being 1 , and a character is assembled in which the parity does not match the peo bit in the cntlb register. however, this status bit is not set until or unless the error character becomes the oldest one in the rxfifo . pe is cleared when software writes a 1 to the efr bit in the cntrla register, and also by reset , in iostop mode, and for asci0 if the dcd0 pin is auto-enabled and is negated (high). asci status registers bit rdrf ovrn rrr/w pe 76 5 4 3 2 1 0 fe re dcd 0 tdre tie r r asci status register 0 (stat0: i/o address = 04h) rrr/w bit rdrf ovrn rr/w pe 76 5 4 3 2 1 0 fe re tdre tie rr asci status register 1 (stat1: i/o address = 05h) rrr/w __ note:
z80180 microprocessor unit 46 ps014004-1106 architecture fe: framing error (bit 4)? a framing error is detected when the stop bit of a character is sampled as 0/space . however, this status bit is not set until or unless the error character becomes the oldest one in the rxfifo . fe is cleared when software writes a 1 to the efr bit in the cntla register, and also by reset , in iostop mode, and for ascio if the dcdo pin is auto-enabled a nd is negated (high). rei: receive interrupt enable (bit 3)? rie must be set to 1 to enable asci receive interrupt requests. when rie is 1 , the receiver requests an in terrupt when a character is received and rdrf is set, but only if neither dma chan nel sets its request-routing field to receive data from this asci. that is, if sm1?0 are 11 and sar17?16 are 10 , or dim1 is 1 and iar17?16 are 10 , then asci1 does not request an interrupt for rdrf . if rie is 1 , either asci requests an interrupt when ovrn , pe or fe is set, and asci0 requ ests an interrupt when dcd0 goes high. rie is cleared to 0 by reset . dcd0 : data carrier detect (bit 2 stat0)? if bit 0 of the interrupt edge register ( ier0 ) is 0 , the dcd0 /cka1 pin features the dcd0 function, and this bit is set to 1 when the pin is high. it is cleared to 0 on the first read of stat0 following the pin's transition from high to low and during reset . when ier0 is 0 , bit 6 of the asext0 register is 0 to select auto-enabling, and the pin is negated (high), the bit 2 of stat1 is not used. tdre: transmit data register empty (bit 1)? tdre = 1 indicates that the tdr is empty and the next transmit data byte is written to tdr . after the byte is written to tdr , tdre is cleared to 0 until the asci transfers the byte from tdr to the tsr and then tdre is again set to 1 . tdre is set to 1 in iostop mode and during reset . on ascio, if the cts0 pin is auto-enabled in the asext0 registers and the pin is high, tdre is reset to 0 . tie: transmit interrupt enable (bit 0)? tie must be set to 1 to enable asci transmit interrupt requests. if tie = 1 , an interrupt is requested when tdre = 1 . tie is cleared to 0 during reset . csio control/status register cntr: i/o address = 0ah? cntr is used to monitor csio status, enable and disable the csio , enable and disable interrupt generation, an d select the data clock speed and source. figure 35. csio control register ef: end flag (bit 7)? ef is set to 1 by the csio to indicate completi on of an 8-bit data transmit or receive operation. if the end interrupt enable ( eie ) bit = 1 when ef is set to 1 , a cpu interrupt request is generated. program access of trdr only occurs if ef = 1 . the csio csio control bit ef eie r/w r/w r/w re 76 5 4 3 21 0 te __ ss2 ss1 ss0 rr/wr/wr/w
z80180 microprocessor unit 47 ps014004-1106 architecture clears ef to 0 when trdr is read or written. ef is cleared to 0 during reset and iostop mode. eie: end interrupt enable (bit 6)? eie is set to 1 to generate a cpu interrupt request. the interrupt request is inhibited if eie is reset to 0 . eie is cleared to 0 during reset . re: receive enable (bit 5)? a csio receive operation is started by setting re to 1 . when re is set to 1 , the data clock is enable d. in internal clock mode, the data clock is out- put from the cks pin. in external clock mode , the clock is input on the cks pin. in either case, data is shifted in on the rxs pin in synchronization with the (internal or external) data clock. after receiving 8 bits of data, the csio automatically clears re to 0 , ef is set to 1 , and an interrupt (if enabled by eie = 1 ) is generated. re and te are never both set to 1 at the same time. re is cleared to 0 during reset and istop mode. transmit enable (bit 4)? a csio transmit operation is started by setting te to 1. when te is set to 1, the data clock is enabled. when in internal clock mode, the data clock is out- put from the cks pin. in external clock mode , the clock is input on the cks pin. in either case, data is shifted out on the txs pin sync hronous with the (internal or external) data clock. after transmitting 8 bits of data, the csio automatically clears te to 0, ef is set to 1 , and an interrupt (if enabled by eie = 1 ) is generated. te and re are never both set to 1 at the same time. te is cleared to 0 during reset and iostop mode. ss2, 1, 0: speed select 2, 1, 0 (bits 2-0)? ss2 , ss1 and ss0 select the csio transmit/ receive clock source and speed. ss2 , ss1 and ss0 are all set to 1 during reset . table 13 lists the csio baud rate selection. after reset , the cks pin is configured as an external clock input ( ss2 , ss1 , ss0 = 1 ). changing these values causes cks to become an output pin and the selected clock is output when transmit or receive operations are enabled. table 13. csio baud rate selection ss2 ss1 ss0 divide ratio 000 20 001 40 010 80 011 160 100 320 101 640 110 1280 111external clock input (less than 20)
z80180 microprocessor unit 48 ps014004-1106 architecture csio transmit/receive data register (trdr: i/o address = 0bh) figure 36. csi/o receive register channel 1r timer data register channel 0l tmdr0l: och figure 37. timer data register channel low timer data register channel 0h tmdr0h: odh figure 38. timer data register channel high asci receive register channel 1r asci receive register channel 1r 0ch timer data register channel high 0dh csio transmit/receive data ? ? ?? ? ?? ? 76 54 32 1 timer data ? ? ?? ? ?? ? 76 54 32 1 timer data ? ? ?? ? ?? ? 76 54 32 1
z80180 microprocessor unit 49 ps014004-1106 architecture timer reload register 0l rldr0l: 0eh figure 39. timer reload register low timer reload register 0h rldr0h figure 40. timer reload register timer control register (tcr) tcr monitors both channels ( prt0 , prt1 ) tmdr status. it also controls enabling and disabling of down counting and interrupt s along with controlling output pin a18 / t out for prt1 . figure 41. timer control register (tcr: i/o address = 10h) timer reload register low 0eh timer reload register 0fh timer control register (tcr: i/o address = 10h) timer reload data ? ? ?? ? ?? ? 76 54 32 1 timer reload data ? ? ?? ? ?? ? 76 54 32 1 bit tif1 tif0 r/w r/w r/w tie1 76 5 4 3 21 0 tie0 toc0 tde1 tde0 r r r/w r/w r/w toc1
z80180 microprocessor unit 50 ps014004-1106 architecture tif1: timer interrupt flag 1 (bit 7)? when tmdr1 decrements to 0 , tif1 is set to 1 , and, when enabled by tie1 = 1 , an interrupt request is generated. tif1 is reset to 0 when tcr is read and the higher or lower byte of tmdr1 is read. during reset , tif1 is cleared to 0 . tif0: timer interrupt flag 0 (bit 6)? when tmdr0 decrements to 0 , tif0 is set to 1 , and, when enabled by tie0 = 1 , an interrupt request is generated tif0 is reset to 0 when tcr is read and the higher or lower byte of tmdr0 is read. during reset , tif0 is cleared to 0 . tie1: timer interrupt enable 1 (bit 5)? when tie0 is set to 1 , tif1 = 1 generates a cpu interrupt request. when tie0 is reset to 0 , the interrupt request is inhibited. during reset , tie0 is cleared to 0 . toc1, 0: timer output control (bits 3, 2)? toc1 and toc0 control the output of prt1 using the multiplexed t out / dreq pin as indicated in table 14 . during reset , toc1 and toc0 are cleared to 0 . if bit 3 of the iar1b register is 1 , the t out function is selected. by programming toc1 and toc0 , the t out / dreq pin can be forced high, low, or toggled when tmdr1 decrements to 0 . tde1, 0: timer down count enable (bits 1, 0)? tde1 and tde0 enable and disable down counting for tmdr1 and tmdr0 , respectively. when tden ( n = 0,1 ) is set to 1 , down counting is stopped and tmdrn is freely read or written. tde1 and tde0 are cleared to 0 during reset and tmdrn do not decrement until tden is set to 1 . asci extension control register channels 0 and 1 asext0 and asext1 the asci extension cont rol register controls functions newly added to the ascis in the z80180 family. all bits in this register reset to 0. table 14. timer output control toc1 toc0 output 0 0 inhibited the t out /dreq pin is not affected by the prt. 0 1 toggled if bit 3 of iar1b is 1, the t out /dreq pin toggles or is set low or high as indicated. 100 111 note:
z80180 microprocessor unit 51 ps014004-1106 architecture figure 42. asci extension control registers, channel 0 and 1 dcd0 dis (bit 6, asci0 only)? if bit 0 of the interrupt edge register is 0 to select the dcd0 function for the dcd0 / cka1 pin, and this bit is 0 , the dcd0 pin auto-enables the asci0 receiver. when the pin is negated/high, the receiver is held in a reset state. if bit 0 of the ier is 0 and this bit is 1 , the state of the dcd -pin has no effect on receiver operation. in either state of this bit, software can read the state of the dcd0 pin in the stat0 register, and the receiver interrupts on a rising edge of dcd0 . cts0 dis (bit 5, asci0 only)? if bit 5 of the system configuration register is 0 to select the cts0 function of the cts0 / rxs pin, and this bit is 0 , then the cts0 pin auto- enables the ascio transmitter, in that when the pin is negated (high), the tdre bit in the stat0 register is forced to 0 . if bit 5 of the system configuration register is 0 and this bit is 1 , the state of the cts0 pin exhibits no effect on the tran smitter. regardless of the state of this bit, software can read the state of the cts0 pin the cntlb0 register. x1 (bit 4)? if this bit is 1 , the clock from the baud rate generator or cka pin is received as a 1x bit clock (sometimes called isochronous mo de). in this mode, receive data on the rxa pin must be synchronized to the clock on the cka pin, regardless of whether cka is an input or an output. if this bit is 0 , the clock from the baud rate generator or cka pin is divided by 16 or 64 per the dr bit in cntlb register, to obtain the actual bit rate. in this mode, receive data on the rxa pin is not required to be synchronized to a clock. brg mode (bit 3)? if the ss2?0 bits in the cntlb register are not 111 , and this bit is 0 , the asci baud rate generator divides phi by 10 or 30, depending on the dr bit in cntlb , and then by a power of two selected by the ss2?0 bits, to obtain the clock that is presented to the transmitter and receiver and that can be output on the cka pin. if ss2?0 are not 111 , and this bit is 1 , the baud rate generator divides phi by twice (the 16-bit value programmed into the time constant registers, plus 2). this mode is identical to the operation of the baud rate generator in the escc. break enable (bit 2)? if this bit is 1 , the receiver detects break conditions and report them in bit 1 , and the transmitter sends brea ks under the control of bit 0 . asci extension control registers, channel 0 and 1 bit dcdo 76 5 4 3 21 0 xi brgo break break send asci extension control register 0(asext0 i/o address = 12h) ctso mode nab break bit 76 5 4 3 21 0 xi brgi break break send mode enab break asci extension control register 1 (asext1 i/o address = 13h) reserved reserved reserved reserved
z80180 microprocessor unit 52 ps014004-1106 architecture break detect (bit 1)? the receiver sets this read-only bit to 1 when an all-zero character with a framing error beco mes the oldest character in the rxfifo . the bit is cleared when software writes a 0 to the efr bit in cntla register, also by reset , by iostop mode, and for ascio if the dcd0 pin is auto-enabled and is negated (high). send break (bit 0)? if this bit and bit 2 are both 1 , the transmitter holds the txa pin low to send a break conditio n. the duration of the break is un der software control (one of the prts or ctcs can be used to time it). this bit resets to 0 , in which state txa carries the serial output of the transmitter. timer data register channel 1l mnemonic tmdr1l:14h figure 43. timer data register channel 1l timer data register channel 1h mnemonic tmdr1h: 15h figure 44. timer data register channel 1h timer data register timer data register 76 54 32 1 0 timer data 76 54 32 1 0 timer data
z80180 microprocessor unit 53 ps014004-1106 architecture timer reload register channel 1l mnemonic rldr1l: 16h figure 45. timer reload register channel 1l timer reload register channel 1h mnemonic rldr1h: 17h figure 46. timer reload register channel 1h timer data register timer data register 76 54 32 1 0 reload data 76 54 32 1 0 reload data
z80180 microprocessor unit 54 ps014004-1106 architecture free running counte r i/o address = 18h mnemonic frc: 18h if data is written into the free running counter, the interval of dram refresh cycle and baud rates for the asci and csi/o are not guaranteed . in iostop mode, the free running counter continues counting down. it is initialized to ffh , during reset. figure 47. timer data register dma source address register channel 0 ( sar0: i/o address = 20h to 22h ) specifies the physical source address for channel 0 transfers. the register contains 20 bits and can specify up to 1024 kb memory addresses or up to 64 kb i/o addresses. channel 0 source ca n be memory, i/o, or memory mapped i/o. for i/o, the most significant bits of this register identify the request handshake signal. dma source address register, channel 0l mnemonic sar0l: address 20h figure 48. dma channel 0l timer data register timer data register 76 54 32 1 0 counting data dma channel 0 address ? ? ?? ? ?? ? 76 54 32 1 ? 0
z80180 microprocessor unit 55 ps014004-1106 architecture dma source address register, channel 0h mnemonic sar0h: address 21h figure 49. dma channel 0h dma source address register channel 0b mnemonics sar0b: address 22h figure 50. dma channel 0b dma destination address register channel 0 ( dar0: i/o address = 23h to 25h ) specifies the physical des tination address for channel 0 transfers. the register contains 20 bits and can specify up to 1024 kb memory addresses or up to 64 kb i/o addresses. ch annel 0 destination can be memory, i/o, or memory mapped i/ o. for i/o, the most significant b its of this register identify the request handshake signal for channel 0. timer data register timer data register dma channel 0 address ? ?? ? ?? ? 76 54 32 1 ? 0 dma channel b address ? ? ?? ? ?? ? ? ?? ? ?? ? 76 54 32 1 ? 0
z80180 microprocessor unit 56 ps014004-1106 architecture dma destination address register channel 0l mnemonic dar0l: address 23h figure 51. dma destination address register channel 0l dma destination address register channel 0h mnemonic dar0h: address 24h figure 52. dma destination address register channel 0h dma destination address register channel 0b mnemonic dar0b: address 25h figure 53. dma destination address register channel 0b dma destination address register channel 0l dma destination address register channel 0h dma destination address register channel 0b dma channel 0l address ? ? ?? ? ?? ? 76 54 32 1 ? 0 dma channel 0h address ? ? ?? ? ?? ? 76 54 32 1 ? 0 dma channel b address ? ?? 3 2 1 0 ?
z80180 microprocessor unit 57 ps014004-1106 architecture in the r1 and z mask, these dma registers are expanded from 4 bits to 3 bits in the package version of cp-68. dma byte count register channel 0 ( bcro: i/o address = 26h to 27h ) specifies the number of bytes to be transferred. this reg- ister contains 16 bits and may specify up to 64 kb transfers. when one byte is transferred, the register is decremented by 1. if n bytes are transferred, n must be stored before the dma operation. all dma count register channels are undefined during reset . dma byte count register channel 0l mnemonic bcr0l: address 26h figure 54. dma byte count register 0l table 15. dma transfer requests a19* a18 a17 a16 dma transfer request xx00dreq0 xx01tdr0 (asci0) xx10tdr1 (asci1) xx11not used dma byte count register note: note: 76 54 32 1 0 counting data
z80180 microprocessor unit 58 ps014004-1106 architecture dma byte count register channel 0h mnemonic bcr0h: address 27h figure 55. dma byte count register 0h dma byte count register channel 1l mnemonic bcr1l: address 2eh figure 56. dma byte count register 1l dma byte count register 0h dma byte count register 1l 76 54 32 1 0 counting data 76 54 32 1 0 counting data
z80180 microprocessor unit 59 ps014004-1106 architecture dma byte count register channel 1h mnemonic bcr1h: address 2fh figure 57. dma byte count register 1h dma memory address register channel 1 ( mar1: i/o address = 28h to 2ah ) specifies the physical memory address for channel 1 transfers, which may also be a destination or source memory address. the register contains 20 bits and may specify up to 1024-kb memory address. dma memory address register, channel 1l mnemonic mar1l: address 28h figure 58. dma memory address register, channel 1l dma byte count register 0h dma memory address register, channel 1l 76 54 32 1 0 counting data dma memory address ? ? ?? ? ?? ? 76 54 32 1 ? 0
z80180 microprocessor unit 60 ps014004-1106 architecture dma memory address register, channel 1h mnemonic mar1h: address 29h figure 59. dma memory address register, channel 1h dma memory address register, channel 1b mnemonic mar1b (address 2a) figure 60. dma memory address register, channel 1b dma i/o address register channel 1 ( iar1: i/o address = 2bh to 2dh ) specifies the i/o address fo r channel 1 transfers, which may also be a destination or source i/o address. the register contains 16 bits of i/o address; its most significant byte identifies the request handshake signal and controls the alternating channel feature. all bits in iar1b reset to 0 . dma memory address register, channel 1h dma dma memory address ? ? ?? ? ?? ? 76 54 32 1 ? 0 dma memory channel b address ? ?? 3 2 1 0 ?
z80180 microprocessor unit 61 ps014004-1106 architecture figure 61. iar ms byte regist er (iarib: i/o address 2dh dma i/o address register channel 1l mnemonic iar1l (address 2b) figure 62. dma i/o addr ess register channel 1l dma i/o address register channel 1h mnemonic iar1h (address 2c) figure 63. dma i/o address register channel 1h iar ms byte register (iarib: i/o address 2dh) dma i/o address register channel 1l dma i/o address register channel 1h bit a/t a/t 76 54 3 2 1 0 f c t out dreq req 1 sel dma i/o channel 1l address ? ? ?? ? ?? ? 76 54 32 1 ? 0 dma i/o address channel 1h ? ? ?? ? ?? ? 76 54 32 1 ? 0
z80180 microprocessor unit 62 ps014004-1106 architecture dma i/o address register channel 1b mnemonic iar1b (address 2d) figure 64. dma i/o address register channel 1b dma status register (dstat) dstat is used to enable and disable dma tr ansfer and dma termination interrupts. dstat also indicates dma transfer status, in other words, completed or in progress. mnemonic dstat (address 30) figure 65. dma status register (dstat: i/o address = 30h) de1: dma enable channel 1 (bit 7)? when de1 = 1 and dme = 1 , channel 1 dma is enabled. when a dma transfer terminates ( bcr1 = 0 ), de1 is reset to 0 by the dmac. when de1 = 0 and the dma interrupt is enabled ( die1 = 1 ), a dma interrupt request is made to the cpu. to perform a software write to de1 , dwe1 must be written with 0 during the same register write access. writing de1 to 0 disables channel 1 dma, bu t dma is restartable. writing de1 to 1 enables channel 1 dma and automatically sets dme (dma main enable) to 1 . de1 is cleared to 0 during reset . de0: dma enable channel 0 (bit 6)? when de0 = 1 and dme = 1 , channel 0 dma is enabled. when a dma transfer terminates ( bcr0 = 0 ), de0 is reset to 0 by the dmac. dma i/o address register channel 1b dma status register (dstat: i/o address = 30h) dma i/o channel b address ? ?? 3 2 1 0 ? bit de1 de0 dwe1 76 5 4 3 2 1 0 r/w r/w w dwe0 die1 die0 dme w r/w r/w r
z80180 microprocessor unit 63 ps014004-1106 architecture when de0 = 0 and the dma interrupt is enabled ( die0 = 1 ), a dma interrupt request is made to the cpu. to perform a software write to de0 , dwe0 must be written with 0 during the same register write access. writing de0 to 0 disables channel 0 dma. writing de0 to 1 enables channel 0 dma and automatically sets dme (dma main enable) to 1 . de0 is cleared to 0 during reset . dwe1 : de1 bit write enable (bit 5)? when performing any software write to de1 , dwe1 must be written with 0 during the same access. dwe1 always reads as 1 . dwe0 : de0 bit write enable (bit 4)? when performing any software write to de0 , dwe0 must be written with 0 during the same access. dwe0 always reads as 1 . die1: dma interrupt enable channel 1 (bit 3)? when die0 is set to 1 , the termination channel 1 dma transfer (indicated when de1 = 0 ) causes a cpu interrupt request to be generated. when die0 = 0 , the channel 0 dma termination interrupt is disabled. die0 is cleared to 0 during reset . die0: dma interrupt enable channel 0 (bit 2)? when die0 is set to 1 , the termination channel 0 of dma transfer (indicated when de0 = 0 ) causes a cpu interrupt request to be generated. when die0 = 0 , the channel 0 dma termination interrupt is dis- abled. die0 is cleared to 0 during reset . dme: dma main enable (bit 0)? a dma operation is on ly enabled when its de bit ( de0 for channel 0, de1 for channel 1) and the dme bit is set to 1 . when nmi occurs, dme is reset to 0 , disabling dma activity during the nmi interrupt service routine. to restart dma, de? and/or de1 must be written with a 1 (even if the contents are already 1 ). this write automatically sets dme to 1 , allowing dma operations to continue. dme cannot be directly written. it is cleared to 0 by nmi or indirectly set to 1 by setting de0 and/or de1 to 1 . dme is cleared to 0 during reset . dma mode register (dmode) dmode is used to set the addressing and transfer mode for channel 0. note:
z80180 microprocessor unit 64 ps014004-1106 architecture mnemonic dmode address 31h figure 66. dma mode register (dmode: i/o address = 31h) dm1, dm0: destination mode channel 0 (bits 5,4)? specifies whether the destination for channel 0 transfers is memory or i/o, and whether the address must be incre- mented or decremented fo r each byte transferred. dm1 and dm0 are cleared to 0 during reset (see table 16 ). sm1, sm0: source mode channel 0 (bits 3, 2)? specifies whether the source for channel 0 transfers is memory or i/o, and whether the address must be incremented or decremented for each byte transferred (see table 17 ). table 18 lists all dma transfer mode combinations of dm0 , dm1 , sm0 , and sm1 . because i/o to/from i/o transfers are not implem ented, 12 combina tions are available. dma mode register (dmode: i/o address = 31h) table 16. channel 0 destination dm1 dm0 memory i/o memory increment/decrement 00memory +1 01memory ?1 1 0 memory fixed 11i/o fixed table 17. channel 0 source sm1 sm0 memory i/o memory increment/decrement 00memory +1 01memory ?1 1 0 memory fixed 11i/o fixed bit dm1 dm0 76 5 4 3 2 1 0 r/w r/w sm1 sm0 mmod r/w r/w r/w
z80180 microprocessor unit 65 ps014004-1106 architecture mmod: memory mode channel 0 (bit 1). when channel 0 is configured for memory to/from memory transfers there is no request handshake signal to control the transfer timing. instead, two automa tic transfer timing modes are selectable: burst ( mmod = 1 ) and cycle steal ( mmod = 0 ). for burst memory to/from memo ry transfers, the dmac takes control of the bus contin uously until the dm a transfer completes (the byte count register is 0 ). in cycle steal mode, the cpu is provided a cycl e for each dma byte transfer cycle until the transfer is completed. for channel 0 dma with i/o source or destination, the selected request handshake signal times the transfer and mmod is ignored. mmod is cleared to 0 during reset . dma/wait control register (dcntl) dcntl controls the insertion of wait states into dmac (and cpu) accesses of memory or i/o. dcntl also defines the request signal for each channel as level or edge sense. dcntl also sets the dma transfer mode for channel 1, which is limited to memory to/from i/o transfers. figure 67. dma/wait control register (dcntl: i/o address = 32h mwi1, mwi0: memory wait insertion (bits 7-6)? specifies the number of wait states introduced into cpu or dmac memory access cycles. mwi1 and mwi0 are set to 1 during reset . iwi1, iwi0: i/o wait insertion (bits 5-4)? specifies the number of wait states introduced into cpu or dmac i/o access cycles. iwi1 and iwi0 are set to 1 during reset . dms1, dms0: dma request sense (bits 3-2)? dms1 and dms0 specify the dma request sense for channel 0 and chan nel 1 respectively. when reset to 0 , the input is level sense. when set to 1 , the input is edge sense. dms1 and dms0 are cleared to 0 during reset . typically, for an input/source devi ce, the associated dms bit must be programmed as 0 for level sense because the device unde rtakes a relatively long period to update its request signal after the dma channel reads data from it in the first of the two machine cycles involved in transferring a byte. an output/destination de vice takes much less time to update its request signal, after the dma channel starts a write operation to it, as the dma/wait control register (dcntl: i/o address = 32h) bit mwi1 iwi0 76 54 3 2 1 0 r/w r/w dms1 dms0 dim1 r/w r/w r/w mwi0 iwi1 dim0 r/w r/w r/w
z80180 microprocessor unit 66 ps014004-1106 architecture second machine cycle of the two cycles involved in transferring a byte. with zero-wait state i/o cycles, which apply only to the ascis, it is impossible for a device to update its request signal in time, and edge sensing must be used. with one-wait-state i/o cycles (the fastest possib le except for the ascis), it is unlikely that an output device is able to update its request in time, and edge sense is required for output to the escc and bidirectional centronics contro ller, and is recommended for external output devices connected to t out / dreq . with two or more wait states in i/o cycles, external output devices on t out / dreq can use edge or level sense de pending on their characteristics; edge sense is still recommended for output on the escc and bidirectional centronics controller. dim1, dim0: dma channel 1 i/o and memory mode (bits 1-0)? specifies the source/destination and address modifier for chan nel 1 memory to/from i/o transfer modes. dim1 and dim0 are cleared to 0 during reset . interrupt vector low register mnemonic: il address 33 bits 7?5 of il are used as bits 7?5 of the synthesized interrupt vector during interrupts for the int1 and int2 pins and for the dmas, ascis, prts , and csio . these three bits are cleared to 0 during reset ( figure 68 ). figure 68. interrupt vector low register (il: i/o address = 33h) table 18. channel 1 transfer mode dim1 dmi0 transfer mode address increment/decrement 00memory i/o mar1 +1, iar1 fixed 01memory i/o mar1?1, iar1 fixed 10i/o memory iar1 fixed, mar1 + 1 11i/o memory iar1 fixed, mar1 ?1 interrupt vector low register (il: i/o address = 33h) bit il 7 il 6 interrupt source dependent code il 5 76 5 4 3 2 1 0 ?? ?? r/w r/w ?? ?? ?? r/w programmable
z80180 microprocessor unit 67 ps014004-1106 architecture int/trap control register mnemonics itc address 34 int/trap control register (itc, i/o address 34h) this register is used in handling trap interrupts and to enable or disable maskable interrupt level 0 and the int1 and int2 pins. figure 69. int/trap control register trap (bit 7)? this bit is set to 1 when an undefined opcode is fetched. trap can be reset under program control by writing it with a 0 , however, it cannot be written with 1 under pro- gram control. trap is reset to 0 during reset . ufo: undefined fetch object (bit 6)? when a trap interrupt occurs, the contents of a ufo allow the starting address of the undefined in struction to be dete rmined. however, the trap may occur on either the second or third byte of the opcode. a ufo allows the stacked program counter ( pc ) value to be correctly adjusted. if ufo = 0 , the first opcode must be interpreted as the stacked pc-1 . if ufo = 1 , the first opcode address is stacked pc-2 . ufo is read-only . ite2, 1, 0: interrupt enable 2, 1, 0 (bits 2-0)? ite2 and ite1 enable and disable the external interrupt inputs int2 and int1 , respectively. ite0 enables and disables interrupts from the on-chip escc, ctcs and bidirectional centronics controller as well as the external interrupt input int0 . a 1 in a bit enables the correspo nding interrupt level while a 0 disables it. a reset clears ite0 to 1 and clears ite1 and ite2 to 0 . trap interrupt the z80180 generates a nonmaskable (not affected by the state of ief1 ) trap interrupt when an undefined opcode fetch occurs. this feature can be used to increase software reli- ability, implement an extended instruction set, or both. trap may occur during opcode fetch cycles and also if an undefined opcode is fe tched during the interrupt acknowledge cycle for int0 when mode 0 is used. bit trap ufo r/w r/w r/w ?? 76 5 4 3 2 1 0 ?? ?? ite2 ite1 ite0 r/w r
z80180 microprocessor unit 68 ps014004-1106 architecture when a trap interrupt occurs, the z80180 operates as follows: 1. the trap bit in the interrupt trap /control ( itc ) register is set to 1 . 2. the current program counter ( pc ) value, reflecting the location of the undefined opcode, is saved on the stack. 3. the z80180 vectors to logical address 0 . if logical address 0000h is ma pped to physical address 00000h, the vector is the same as for reset. in this case, testing th e trap bit in itc reveals whether the restart at physical address 0000 0h was caused by reset or trap. all trap interrupts occur after fetching an undefi ned second opcode byte following one of the prefix opcodes cbh , ddh , edh , or fdh , or after fetching an undefined third opcode byte following one of the double-prefix opcodes ddcbh or fdcbh . the state of the undefined fetch object ( ufo ) bit in itc allows trap software to correctly adjust the stacked pc , depending on whether the second or third byte of the opcode gener- ated the trap . if ufo = 0 , the starting address of the inva lid instruction is equal to the stacked pc-1 . if ufo = 1 , the starting address of the invalid instruction is equal to the stacked pc-2 . figure 70. trap timing?2 nd opcode undefined trap timing?2 nd op code undefined note: t 1 t 2 t 3 t tp t i t i t i t i t i t 1 t 2 t 3 t 2 t 3 t 1 t 1 t 2 a 0 ?a 18 (a 19 ) d 0 ?d 7 pc 0000h sp-1 undefined mreq m1 rd wr t 3 sp-2 opcode pc h pc l 2nd opcode fetch cycle pc stacking opcode fetch cycle restart from 0000h
z80180 microprocessor unit 69 ps014004-1106 architecture figure 71. trap timing?3 rd opcode undefined refresh control register mnemonic rcr (address 36) figure 72. refresh control register (rca: i/o address = 36h) the rcr specifies the interval and length of refresh cycles, while enabling or disabling the refresh function. refe: refresh enable (bit 7)? refe = 0 disables the refresh controller, while refe = 1 enables refresh cycle insertion. refe is set to 1 during reset . refw: refresh wait (bit 6)? refw = 0 causes the refresh cycle to be two clocks in duration. refw = 1 causes the refresh cycle to be thr ee clocks in duration by adding a refresh wait cycle ( trw ). refw is set to 1 during reset . trap timing?3 rd op code undefined refresh control register (rca: i/o address = 36h) t 1 t 2 t 3 t 1 t 2 t tp t 3 t i t i t 1 t 2 t 3 t 2 t 3 t 1 t 1 t 2 a 0 ?a 18 (a 19 ) d 0 ?d 7 pc 0000h sp-1 undefined mreq m1 rd wr t 3 sp-2 opcode pc-1 h pc-1 l 3nd opcode fetch cycle pc stacking opcode fetch cycle restart memory ix + d, iy + d t i t i read cycle from 0000h reserved ? ? ?? ?? ? 76 54 32 1 cyc1 cyc0 refw refe - ? 0
z80180 microprocessor unit 70 ps014004-1106 architecture cyc1, 0: cycle interval (bit 1,0)? cyc1 and cyc0 specify the interval (in clock cycles) between refresh cycles. in the case of dynamic rams requiring 128 refresh cycles every 2 ms (or 256 cycles in every 4 ms), the requir ed refresh interval is less than or equal to 15.625 s. the underlined values indicate the best refresh in terval depending on cpu clock frequency. cyc0 and cyc1 are cleared to 0 during reset (see table 19 ). refresh control and reset after reset , based on the initialized value of rcr , refresh cycles occur with an interval of 10 clock cycles and be 3 clock cycles in duration. dynamic ram refresh operation 1. refresh cycle insertion is stopped when the cpu is in the following states: a. during reset b. when the bus is released in response to busreq c. during sleep mode d. during wait states 2. refresh cycles are suppressed when the bus is released in response to busreq . however, the refresh timer continues to operat e. the time at which the first refresh cycle occurs after the z80180 reacquires the bu s depends on the refresh timer, and possesses no timing relationship with the bus exchange. 3. refresh cycles are suppressed during sleep mode. if a refresh cycle is requested during sleep mode, the refresh cycle request is internal ly latched (until replaced with the next refresh request). the latched refresh cycle is inserted at the end of the first machine cycle after sleep mode is exited. after this initial cycle, the time at which the next refresh cycle occurs depends on the refresh ti me and carries no relati onship with the exit from sleep mode. table 19. dram refresh intervals insertion interval time interval cyc1 cyc0 ?: 10 mhz 8 mhz 6 mhz 4 mhz 2.5 mhz 0 0 10 states (1.0 s)* (1.25 s)* 1.66 s 2.5 s 4.0 s 0 1 20 states (2.0 s)* (2.5 s)* 3.3 s 5.0 s 8.0 s 1 0 40 states (4.0 s)* (5.0 s)* 6.6 s 10.0 s 16.0 s 1 1 80 states (8.0 s)* (10.0 s)* 13.3 s 20.0 s 32.0 s *calculated interval.
z80180 microprocessor unit 71 ps014004-1106 architecture 4. the refresh address is incremented by one fo r each successful refresh cycle, not for each refresh. independent of the number of missed refresh requests, each refresh bus cycle uses a refresh address incremented by one from that of the previous refresh bus cycles. mmu common base register mnemonic cbr address 38 mmu common base register (cbr)? cbr specifies the base address (on 4-kb boundaries) used to generate a 20-bit physical address for common area 1 accesses. all bits of cbr are reset to 0 during reset . figure 73. mmu bank base regi ster (bbr: i/o address = 39h) mmu bank base register (bbr) mnemonic bbr address 39 bbr specifies the base address (on 4-kb boundaries) used to generate a 19-bit physical address for bank area accesses. all bits of bbr are reset to 0 during reset . figure 74. mmu bank base regi ster (bbr: i/o address = 39h) mmu bank base register (bbr: i/o address = 39h) mmu bank base register (bbr: i/o address = 39h) bit cb7 cb6 r/w cb5 76 5 4 3 21 0 cb4 cb2 cb1 cb0 r/w cb3 r/w r/w r/w r/w r/w r/w bit bb7 bb6 r/w bb5 76 5 4 3 21 0 bb4 bb2 bb1 bb0 r/w bb3 r/w r/w r/w r/w r/w r/w
z80180 microprocessor unit 72 ps014004-1106 architecture mmu common/bank area register (cbar) mnemonic cbar address 3a cbar specifies boundaries within the z80180 64-kb logical ad dress space for up to three areas: common area, bank area and common area 1. figure 75. mmu common/bank area re gister (cbar: i/o address = 3 ah ca3?ca0:ca (bits 7-4)? ca specifies the start (low) address (on 4 kb boundaries) for the common area 1, and also determines the most recent address of the bank area. all bits of ca are set to 1 during reset . ba?ba0 (bits 3-0)? ba specifies the start (low) address (on 4-kb boundaries) for the bank area, and also determines the most recen t address of the common area 0. all bits of ba are set to 1 during reset . operation mode control register mnemonic omcr address 3e the z80180 is descended from two different ance stor processors, zilog's original z80 and the hitachi 64180. the operating mode mmu common/bank area register (cbar: i/o address = 3 ah bit ca3 ca2 r/w ca1 76 5 4 3 21 0 ca0 ba2 ba1 ba0 r/w ba3 r/w r/w r/w r/w r/w r/w
z80180 microprocessor unit 73 ps014004-1106 architecture control register (omcr) can be programmed to select between certain differences between the z80 and the 64180. figure 76. operating control register (omcr: i/o address = 3eh m1e (m1 enable)? this bit controls the m1 output and is set to a 1 during reset. when m1e = 1 , the m1 output is asserted low during the opcode fetch cycle, the int0 acknowledge cycle, and the first machine cycle of the nmi acknowledge. on the z80180, this choice makes the processor fetch a reti instruction one time only, and when fetching a reti from zero-wait-state memory, uses three clock machine cycles which are not fully z80-timing compatible, but are compatible with the on-chip ctcs. when mie = 0 , the processor does not drive m1 low during instruction fetch cycles. after fetching a reti instruction one time only with normal timing, the processor refetches the instruction using fully z80-compatible cycles that include driving m1 low. as a result, some external z80 peripherals may require properly decoded reti instruction. figure 77. reti instruction sequence with mie=0 operating control omcr: i/o address = 3eh) d7 reserved d6 d5 ? ioc (r/w) m1te (w) m1e (r/w) ? ?? ? t 1 t 2 t 3 t 1 t 2 t 3 t i t i t i t 1 t 2 t 3 t 1 t 2 t 3 t i t i a 0 ?a 18 (a 19 ) d 0 ?d 7 pc pc+1 pc pc+1 edh 4dh edh 4dh mreq m1 rd st
z80180 microprocessor unit 74 ps014004-1106 architecture i/o control register (icr) icr allows relocating of the internal i/o addresses. icr also controls enabling/disabling of the iostop mode ( figure 78 ). figure 78. i/o control register (icr: i/o address = 3fh) ioa7, 6: i/o address relocation (bits 7,6) ioa7 and ioa6 relocate internal i/o as illustrated in figure 79 . the high-order 8 bits of 16-bit internal i/o address are always 0. ioa7 and ioa6 are cleared to 0 during reset . figure 79. i/o address relocation iostp: iostop mode (bit 5)? iostop mode is enabled when iostp is set to 1 . normal i/o operation resumes when iostop is reprogrammed or reset to 0 . i/o control register (icr: i/o address = 3fh) ioa7 ioa6 ? ? ?? iostp bit 7 6543210 ? r/w r/w r/w note: ioa7?ioa6 = 1 1 ioa7?ioa6 = 1 0 ioa7? ioa6 = 0 1 ioa7?ioa6 = 0 0 00ffh 00c0h 00bfh 0080h 0070h 0040h 003fh 0000h
z80180 microprocessor unit 75 ps014004-1106 package information package information figure 80. 80-pin qfp package diagram
z80180 microprocessor unit 76 ps014004-1106 package information figure 81. 64-pin dip package diagram
z80180 microprocessor unit 77 ps014004-1106 package information figure 82. 68-pin plcc package diagram 68-pin plcc package diagram
z80180 microprocessor unit 78 ps014004-1106 ordering information ordering information for fast results, contact your lo cal zilog sales office for assistance in ordering the part required. codes example: the z80180 is a 10-mhz dip, 0 oc to 70 oc, with plastic standard flow. table 20. ordering information z80180 6, 8, 10, 20, 33 mhz z8018010fsc z8018010psc z8018010vsc package f = plastic quad flatpack p = plastic dual in line v = plastic leaded chip carrier temperature s = 0 c to +70 c speed 6 = 6 mhz 8 = 8 mhz 10 = 10 mhz environmental c = plastic standard z zilog prefix 80180 product number 10 speed p package s temperature c environmental flow
ps014004-1106 customer support z80180 microprocessor unit 79 customer support if you experience any problems while opera ting this product, please check the zilog knowledge base: http://kb.zilog.co m/kb/okbmain.asp if you cannot find an answer or have further questions, please see the zilog technical support web page: http://support.zilog.com

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